The advent of programmable logic devices (PLDs) represented a significant advance in solid state electronics. With PLDs, it became possible to greatly simplify circuit design, to substitute a single device in place of several, to shrink circuit size, and to reduce power consumption. Traditionally, PLDs have been used in combinational circuits such as address decoders, as well as sequential circuits involving bus artibration schemes. During the past several years, advances and improvements in PLD architectures have made possible devices having greater complexity, density, and speed. In spite of the improvements, PLD architecture still suffers from significant limitations.
A typical PLD combines a user-programmable AND array, a fixed or programmable OR gate or array, a macrocell having output registers or buffers, a feedback path from the output registers or buffers to the AND array, and output terminals.
A programmable logic device with a registered mode macrocell has two logical OR arrays, each of which provides a sum of products term output as an input to the macrocell. The sum of products term output from the first OR array is fed to a register (also called a flip-flop or memory element). The register receives a clock signal input, and output signals from the register are synchronized with the clock signal in order to provide a registered mode output. The sum of products term output from the second OR array does not pass through a register, and is referred to an a combinatorial or combinational mode output.
The existence of a feedback path makes PLDs ideal candidates for state machine implementations. Although a feedback path permits an architecture with which a state machine may be implemented, feedback paths have heretofore been rather inflexible. Specifically, in prior art PLDs having a registered mode macrocell, there is no provision for disabling the output driver in order that the output terminal may be used for the input of external signals used to control the AND array. FIG. 1 depicts a prior art PLD having such an inflexible feedback architecture. When operating in an output mode, the sum of products output from programmable OR array 10 is coupled to output terminal 14 via register 11 and tri-state output buffer 12. Simultaneously, input buffer 16 receives the complement of the registered OR signal via feedback line 18, and transmits this signal to the AND array 15. There is no provision for utilizing output terminal 14 to send external signals to the AND array 15.
In a PLD having a registered mode macrocell, the ability to disable output buffer 12 and utilize output terminal 14 for the input of control signals to the AND array would be very useful. For example, a pre-loadable down counter is often used in a state machine. Thus, it may be desirable for a host computer to access memory for a 256 count and sample the count as it approaches zero. The counter may then be reset to a 172 count which provides a wait period for video boot-up.
For the purpose of providing additional background material which may, in certain respects, illustrate the state of the art, the following books are incorporated herein by reference: Programmable Logic Handbook, fourth edition, Monolithic Memories, Inc., 2175 Mission College Blvd., Santa Clara, Calif.; and Practical Design Using Programmable Logic, by S. Pellerin and M. Holley, Prentice Hall, Library of Congress No. TK7872 .L64 P44, 1991.